Sequential-Logic-Circuit

Sequential Clock Circuit

There are multiple combinational logic circuits in a circuit. And sequential logic circuit connects them into a single one, which is synchorized by a clock.

The critical path is the longest delay betwwen any two registers in a circuit. The clock period must be longer be longer than this critical path, or the signal will not propagate properly to that next register.

So the max frequency of the circuit is limited by how much time needed to get correct Next State to Register. (\(t_{setup}\) constraint)

The structure of circuit should like this:

input -> Combinational -> output 
    --> Logic Circuit --
    |                  | (Next State)
    ---   Register <----

So when you overclock, you actually force your machine to break the limit of Max Clock Frequency. That's unsafe and untable.

You can: - add extra register to shorten critical path. Meanwhile, it may require more period. However, that's fine for pipeline. More latency, but more throughtput too.

Pipielining tends to improve performance.

Finite State Machine

State transitions are controlled by the clock, On each clock cycle the machine checks, generate new state and new output.

Register holds a representation of the FSM's state - Must assign a unique bit pattern for each state - Output is present/current state (PS/CS) - Input is next state (NS)

Combinational Logic implements transition function here.