DMA serves asa real solution for I/O problems.
- Device controller transfers data directly to/from memory without involving the processor.
- Only interrupts once per page (large) once transfer is complete.
The incoming procedure:
- Receive interrupt from device
- CPU takes interrupt, begins transfer (instructs DMA to place data at certain address)
- Device/DMA engine handle the transfer (CPU is free to execute other things)
- Upon completion, Device/DMA engine interrupt the CPU again
The outgoing procedure:
- CPU decides to initiate transfer, confirms that external device is ready.
- CPU takes interrupt, begins transfer (instructs DMA to place data at certain address)
- Device/DMA engine handle the transfer (CPU is free to execute other things)
- Device/DMA engine interrupt the CPU again to signal completion
Cache-coherency
DMA writes to memory, leading to incoherency with cache. Here we can see DMA as another processor core, whose coherency has been solved by most modern multiprocessors.
DMA and CPU Sharing Memory
Cycle Stealing mode
- DMA Engine transfers a byte, releases control, then repeats
Transparent Mode (Maybe best)
- DMA transfer only occurs when CPU is not using the system bus